ESP-IDF has a bunch of equipment deliberation APIs that permit clients to control peripherals at various degrees of reflection, instead of interfacing with equipment utilizing just ESP-IDF drivers. The ESP-IDF equipment reflection will be helpful for clients who are composing superior uncovered metal drivers, or for those attempting to port an ESP chip to another stage. Get the full details of what is physical capital and where does this term use?
Equipment deliberation APIs (with the exception of drivers and xxx_types.h) ought to be viewed as a trial highlight, in this manner can’t be viewed as a public API. The Hardware Abstraction API doesn’t consent to the API renaming limitations of ESP-IDF’s forming plan. As such, it is conceivable that the equipment reflection API might change between non-significant delivery forms. Albeit this archive fundamentally centers around equipment deliberation of peripherals (eg, UART, SPI, I2C), a few layers of equipment reflection reach out to different parts of equipment also (for instance, a few elements of the CPU somewhat are conceptual).
Equipment deliberation in ESP-IDF is involved lower layers, requested from a low degree of reflection (nearer to the equipment) to a more elevated level (a long way from the equipment). The LL layer and the HAL are totally held inside the HAL part. Each layer is reliant upon the layer underneath it (ie, the driver relies upon HAL, HAL relies upon LL, LL relies upon register header documents).
For a specific fringe xxx, its equipment reflection will for the most part incorporate the header documents depicted in the table beneath. Target explicit records will have an alternate execution for each focus (that is, a different duplicate for each chip). Be that as it may, the #include order will in any case be target-free (i.e., the equivalent for various targets) on the grounds that the form framework will consequently incorporate the right form of the header and source documents. This header contains a rundown of C macros determining the different capacities of the ESP32’s fringe xxx. The equipment abilities of the fringe incorporate things like the number of channels, DMA support, equipment FIFO/cushion length, and so forth
The two headers contain a portrayal of fringe registers in a C design and a C large-scale design, separately. Clients can work a fringe at the register level through both of these two header records. In the event that a few signs of a fringe are planned to a specific pin of ESP32, their planning is characterized in this header as C macros. This header is principally utilized as an accommodation header document to naturally incorporate xxx_caps.h, xxx_struct.h, and xxx_reg.h. This header contains type definitions and macros that are divided among the LL, HAL, and driver layers. Besides, it is viewed as a public API so it very well may be incorporated by the application level. Shared sorts and definitions are typically identified with non-execution explicit ideas like the accompanying:
Convention-related sorts/macros like edge, mode, normal transport speed, and so on . This header contains the Low Level (LL) layer of equipment deliberation. The LL Layer API is principally used to digest away register activities into read-only works. The Hardware Abstraction Layer (HAL) is utilized to extract away fringe activity ventures into assignments (e.g., perusing a cushion, beginning a transmission, taking care of an occasion, and so forth) HAL is based on top of the LL layer. The driver layer is the most significant level of equipment reflection of ESP-IDF. Driver layer APIs are to be called from ESP-IDF applications and use OS natives inside. Hence, driver layer APIs are occasion-driven and can be utilized in a multi-string climate.
Ll (Low Level) Layer
The main role of the LL layer is to extract away register field access into all the more effectively justifiable capacities. LL works basically decipher the different in/out contentions into the fringe’s register fields as getting/set capacities. All vital bit moving, covering, balancing, and endianness of register fields should be taken care of by the LL capacities.
The code piece above shows the particular LL work for fringe xxx. LL works for the most part have the accompanying attributes: All LL capacities are characterized as static inline so that there is negligible overhead when calling these capacities because of compiler advancements. The primary contention should be a pointer of type xxx_dev_t. The xxx_dev_t type is a design that addresses fringe registers, in this way the main contention is consistently a pointer to the beginning location of the fringe’s registers. Note that sometimes where the fringe has different channels with a similar register format, xxx_dev_t *hw may rather highlight the registers of a specific channel.
LL capacities should be little and are deterministic much of the time. As such, the most pessimistic scenario runtime of a LL capacity is still up in the air at gathering time. Subsequently, any circles in LL capacities should be delimited; However, there are at present a few special cases for this standard. LL capacities are not strung safe, it is the obligation of the upper layers (driver layer) to guarantee that registers or register fields are not gotten to at the same time. In this article, you must also get to know in brief the CID full form.
Hal (Hardware Abstraction Layer)
The HAL layer models the working system of a fringe as a bunch of normal advances, where each progression has a related capacity. For each stage, the subtleties of a fringe’s register execution (ie, which registers should be set/perused) are covered up (disconnected away) by the HAL. By displaying fringe tasks as a bunch of utilitarian advances, any minor equipment execution contrasts of peripherals between various targets or chip variants can be overwhelmed by HAL (for example taken care of straightforwardly). All in all, the HAL API for a specific fringe will continue as before across most objective/chip forms.